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edi2cg472128v 1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com the edi2cg472128vxxd2 is a synchronous/synchronous burst sram, 84 position dual key; double high dimm (168 contacts) module, organized as 4x128kx72. the module contains eight (8) synchronous burst ram devices, packaged in the industry stan- dard jedec 14mmx20mm tqfp placed on a multilayer fr4 substrate. the module architecture is defined as a sync/sync burst, flow-through, with support for either linear or sequential burst. this module provides high performance, 2-1-1-1 accesses when used in burst mode, and used as a synchronous only mode, provides a high performance cost advantage over bicmos asyn- chronous device architectures. synchronous only operations are performed via strapping adsc\ low, and adsp\ / adv\ high, which provides for ultra fast accesses in read mode while providing for internally self-timed early writes. synchronous/synchronous burst operations are in relation to an externally supplied clock, registered address, registered global write, registered enables as well as an asynchronous output enable. this module has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as quad words in both read and write operations. features n 4x128kx72 synchronous, synchronous burst n access speed(s): t khqv = 8.5, 10, 12, 15ns n flow-through architecture n linear and sequential burst support via mode pin n clock controlled registered module enable (em\) n clock controlled registered bank enables (e 1 \, e 2 \, e 3 \, e 4 \) n clock controlled byte write mode enable (bwe\) n clock controlled byte write enables (bw 1-8 \) n clock controlled registered address n clock controlled registered global write (gw\) n aysnchronous output enable (g\) n internally self-timed write n individual bank sleep mode enables (zz 1 , zz 2 , zz 3 , zz 4 ) n gold lead finish n 3.3v 10% operation n common data i/o n high capacitance (30pf) drive, at rated access speed n single total array clock n multiple vcc and vss march 1998 rev. 0 eco# 10038 4x128kx72, 3.3v sync/sync burst sram dual key dimm
edi2cg472128v 2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com pin configuration dq 0-63 input/output bus dqp 0-7 parity bits a 0-6 address bus e 1 \, e 2 \, synchronous bank enables e 3 \, e 4 \ bwe\ byte write mode enable bw 1 - 8 \ byte write enables clk array clock gw\ synchronous global write enable g\ asynchronous output enable zz 1 , zz 2 , synchronous bank enables zz 3 , zz 4 vcc 3.3v power supply vss ground nc no connect pin names pin symbols pin pin pin pin front front back back v ss 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 a 16 a 14 a 12 a 10 v cc rfu v ss mode rfu v cc 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 v ss a 17 a 15 v cc a 11 v ss rfu v ss clk v ss bwe\ v cc v ss dq 19 v ss dq 24 dq 25 dqp 2 v ss dq 31 dq 30 v ss nc v cc a 13 dq 20 a 0 a 2 a 4 a 6 a 1 a 3 a 5 a 7 nc v cc dq 16 dq 23 dq 22 dq 17 dq 18 dq 21 v cc dqp 3 v cc a 8 bw 8 \ bw 7 \ v ss a 9 bw 6 \ bw 5 \ v ss zz 2 e 4 \ e 2 \ em\ gw\ bw 4 \ bw 3 \ adsc\ adsp\ e 1 \ e 3 \ g\ bw 2 \ bw 1 \ adv\ dq 26 dq 27 v ss nc v cc dq 32 dq 33 dq 34 dq 35 v ss v cc dq 40 dq 41 dq 42 dq 43 v ss dq 29 dq 28 v ss dqp 4 v cc dq 39 dq 38 dq 37 dq 36 v ss dqp 5 v cc dq 47 dq 46 dq 45 10 11 12 13 14 15 16 17 18 dq 44 v ss v cc dq 0 dq 1 dq 2 dq 3 v ss v cc dq 8 dq 9 dq 10 dq 11 v ss dqp 0 v cc dq 7 dq 6 dq 5 dq 4 v ss dqp 1 v cc dq 15 dq 14 dq 13 dq 12 v ss nc v cc dq 48 dq 49 dq 50 dq 51 v ss v cc dq 56 dq 57 dq 58 dq 59 v ss dqp 6 v cc dq 55 dq 54 dq 53 dq 52 v ss dqp 7 v cc dq 63 dq 62 dq 61 dq 60 v ss zz 3 zz 1 zz 4 1 2 3 4 5 6 7 8 9 rfu
edi2cg472128v 3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com functional block diagram g\ gw\ e 1 \ gw\ g\ e\ dq e 3 \ e 2 \ e 4 \ clk clk a 0-16 dq 0-31 dqp 0-3 128kx36 dqp dqp 4-7 zz zz1 zz 2 zz 3 zz 4 u1 gw\ g\ e\ dq clk 128kx36 dqp zz u3 gw\ g\ e\ dq clk 128kx36 dqp zz u2 gw\ g\ e\ dq clk 128kx36 dqp zz u4 gw\ g\ e\ dq clk 128kx36 dqp zz u5 gw\ g\ e\ dq clk 128kx36 dqp zz u6 gw\ g\ e\ dq clk 128kx36 dqp zz u8 gw\ g\ e\ dq clk 128kx36 dqp zz u7 dq 32-63
edi2cg472128v 4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com pin descriptions dimm pins symbol type description 2, 87, 4, 89, 7, 92 a 0-16 input addresses: these inputs are registered and must meet the setup and hold times around the rising edge of clk. the 9, 94, 12, 96, 10 synchronous burst counter generates internal addresses associated with a 0 and a 1 , during burst and wait cycle. 93, 8, 91, 5, 88, 3 107, 106, 23, bw 1 \, bw 1 \, input byte write: a byte write is low for a write cycle and high for a read cycle. bw 0 / controls dq 0-7 and dqp 0 , bw 1 \ 22, 109, 108, bw 3 \, bw 4 \, synchronous controls dq 8-15 and dqp 1 . bw 2 \ controls dq 16-23 and dqp 2 . bw 3 \ controls dq 24-31 and dqp 3 . bw 4 \ controls dq 32-39 25, 24 bw 5 \, bw 6 \, and dqp 4 . bw 5 \ controls dq 40-47 and dqp 5 . bw 6 \ controls dq 48-55 and dqp 6 . bw 7 \ controls dq 56-64 and dqp 7 . bw 7 \, bw 8 \ 104 bwe\ input write enable: this active low input gates byte write operations and must meet the setup and hold times around the synchronous rising edge of clk. 19 gw\ input global write: this active low input allows a full 72-bit write to occur independent of the bwe\ and bwx\ lines and synchronous must meet the setup and hold times around the rising edge of clk. 101 clk input clock: this signal registers the addresses, data, chip enables, write control and burst control inputs on its risin g edge. synchronous all synchronous inputs must meet setup and hold times around the clocks rising edge. 98, 15, e 1 \, e 2 \ input bank enables: these active low inputs are used to enable each individual bank and to gate adsp\. 99,14 e 3 \, e 4 \ synchronous 103 g\ input output enable: this active low asynchronous input enables the data output drivers. 111 adv\ input address status processor: this active low input is used to control the internal burst counter. a high on this pin synchronous generates wait cycle (no address advance). 27 adsp\ input address status processor: this active low input, along with el\ and eh\ being low, causes a new external synchronous address to be registered and a read cycle is initiated using the new address. 26 adsc\ input address status controller: this active low input causes device to be de-selected or selected along with new synchronous external address to be registered. a read or write cycle is initiated depending upon write control inputs. 17 mode input static mode: this input selects the burst sequence. a low on this pin selects linear burst. a nc or high on this pin selects interleaved burst. 36, 50, zz 1 , zz 2 , input snooze: these active high inputs put the individual banks in low power consumption standby mode. 64, 78 zz 3 , zz 4 asynchronous for normal operation, this input has to be either low or nc (no connect). various dq 0-63 input/output data inputs/outputs: first byte is dq 0-7 , second byte is dq 8-15 , third byte is dq 16-23 , fourth byte is dq 24-31 , fifth byte is dq 32-39 , sixth byte is dq 40-47 , seventh byte is dq 48-55 and the eight byte is dq 56-64 . 113, 120, 127, dqp 0-7 input/output parity inputs/outputs: dqp 0 is parity bit for dq 0-7 . dqp 1 is parity bit for dq 8-15 . dqp 2 is parity bit for dq 16-23 . dqp 3 134, 141, 148, is parity bit for dq 24-31 . dqp 4 \ is parity bit for dq3 2-39 . dqp 5 is parity bit for dq 40-47 . dqp 6 \ is parity bit for dq 48-55 . 155, 162 dqp 7 is parity bit for dq 56-64 and dqp 7 . in order to use the device configured as a 128k x 64, the parity bits need to be tied to vss through a 10k ohm resistor. various vcc supply core power supply: +3.3v -5%/+10% various vss ground ground
edi2cg472128v 5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com synchronous burst - truth table operation e1\ e2\ e3\ e4\ adsp\ adsc\ adv\ gw\ g\ clk dq addr. used deselected cycle, power down; bank 1 h x * * x l x x x l-h high-z none deselected cycle, power down; bank 2 x h * * x l x x x l-h high-z none read cycle, begin burst; bank 1 l h * * l x x x l l-h q external read cycle, begin burst; bank 1 l h * * l x x x h l-h high-z external read cycle, begin burst; bank 2 h l * * l x x x l l-h q external read cycle, begin burst; bank 2 h l * * l x x x h l-h high-z external write cycle, begin burst; bank 1 l h * * h l x l x l-h d external write cycle, begin burst; bank 2 h l * * h l x l x l-h d external read cycle, begin burst; bank 1 l h * * h l x h l l-h q external read cycle, begin burst; bank 1 l h * * h l x h h l-h high-z external read cycle, begin burst; bank 2 h l * * h l x h l l-h q external read cycle, begin burst; bank 2 h l * * h l x h h l-h high-z external read cycle, continue burst; bank 1 x h * * x h l h l l-h q next read cycle, continue burst; bank 1 x h * * x h l h h l-h high-z next read cycle, continue burst; bank 2 h x * * x h l h l l-h q next read cycle, continue burst; bank 2 h x * * x h l h h l-h high-z next read cycle, continue burst; bank 1 h h * * x h l h l l-h q next read cycle, continue burst; bank 1 h h * * x h l h h l-h high-z next read cycle, continue burst; bank 2 h h * * x h l h l l-h q next read cycle, continue burst; bank 2 h h * * x h l h h l-h high-z next write cycle, continue burst; bank 1 x h * * h h l l x l-h d next write cycle, continue burst; bank 1 h h * * x h l l x l-h d next write cycle, continue burst; bank 2 h x * * h h l l x l-h d next write cycle, continue burst; bank 2 h h * * x h l l x l-h d next read cycle, suspend burst; bank 1 x h * * h h h h l l-h q current read cycle, suspend burst; bank 1 x h * * h h h h h l-h high-z current read cycle, suspend burst; bank 2 h x * * h h h h l l-h q current read cycle, suspend burst; bank 2 h x * * h h h h h l-h high-z current read cycle, suspend burst; bank 1 h h * * x h h h l l-h q current read cycle, suspend burst; bank 1 h h * * x h h h h l-h high-z current read cycle, suspend burst; bank 2 h h * * x h h h l l-h q current read cycle, suspend burst; bank 2 h h * * x h h h h l-h high-z current write cycle, suspend burst; bank 1 x h * * h h h l x l-h d current write cycle, suspend burst; bank 1 h h * * x h h l x l-h d current write cycle, suspend burst; bank 2 h x * * h h h l x l-h d current write cycle, suspend burst; bank 2 h h * * x h h l x l-h d current *all truth table functions repeat for bank 3 (e 3 \) and bank 4 (e 4 \)
edi2cg472128v 6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com dc electrical characteristics - read cycle recommended dc operating conditions absolute maximum ratings* *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on vcc relative to vss -0.5v to +4.6v vin -0.5v to vcc +0.5v storage temperature -55 c to +125 c operating temperature (commercial) 0 c to +70 c operating temperature (industrial) -40 c to +85 c short circuit output current 10 ma parameter sym min typ max units supply voltage v cc 3.14 3.3 3.6 v supply voltage v ss 0.0 0.0 0.0 v input high v ih 2.2 3.0 v cc +0.3 v input low v il -0.3 0.0 0.3 v input leakage il i -2 1 2 m a output leakage ilo -2 1 2 m a max description symbol typ 8.5 10 12 15 units power supply current icc 1 2.0 2.9 2.7 2.7 2.5 a power supply current icc 875 1.8 1.8 1.3 1.3 a device selected,no operation snooze mode icczz 500 700 700 700 700 ma cmos standby icc 3 270 300 350 350 350 ma clock running-deselect icck 900 1.1 1.1 1.0 1.0 a synchronous only - truth table operation e1\ e2\ e3\ e4\ gw\ g\ zz clk dq synchronous write-bank 1 l h h h l h l - high-z synchronous read-bank 1 l h h h h l l - synchronous write-bank 2 h l h h l h l - high-z synchronous read-bank 2 h l h h h l l - synchronous write-bank 3 h h l h l h l - high-z synchronous read-bank 3 h h l h h l l - synchronous write-bank 4 h h h l l h l - high-z synchronous read-bank 4 h h h l h l l - snooze mode x x x x x x h x high-z ac test circuit ac test conditions 50 w vt = 1.5v output z0 = 50 w z0 = 50 w parameter i/o unit input pulse levels v ss to 3.0 v input and output timing levels 1.25 v output test equivalencies see figure, at left ac output load equivalent 1.25v
edi2cg472128v 7 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com synchronous only read cycle read cycle timing parameters *tbd 8.5ns 10ns 12ns 15ns description sym min max min max min max min max units clock cycle time t khkh * * 15 15 20 ns clock high time t khkl ** 5 5 6 ns clock low time t klkh ** 5 5 6 ns clock to output valid t khqv * * 10 12 15 ns clock to output invalid t khqx1 ** 3 3 3 ns clock to output low-z t khqx ** 4 4 4 ns output enable to output valid t glqv **556ns output enable to output low-z t glqx ** 0 0 0 ns output enable to output high-z t ghqz **555ns address setup t avkh * * 2.5 2.5 2.5 ns bank enable setup t evkh * * 2.5 2.5 2.5 ns address hold t khax * * 1.0 1.0 1.0 ns bank enable hold t khex * * 1.0 1.0 1.0 ns t khqx dq read cycle q(addr 1) q(addr 1) q(addr 2) t khqz gw\ oe\ addr ce\ clk t khqv addr 1 addr 2 addr 1 t khkh t klkh t khkl t glqx back to back read t khqx1 t glqv t khax t avkh ex\ g\ first second third fourth address address address address (external) (internal) (internal) (internal) a..a00 a..a01 a..a10 a..a11 a..a01 a..a00 a..a11 a..a10 a..a10 a..a11 a..a00 a..a01 a..a11 a..a10 a..a01 a..a00 burst address table (mode = v ss ) burst address table (mode = nc/v cc ) first second third fourth address address address address (external) (internal) (internal) (internal) a..a00 a..a01 a..a10 a..a11 a..a01 a..a10 a..a11 a..a00 a..a10 a..a11 a..a00 a..a01 a..a11 a..a00 a..a01 a..a10
edi2cg472128v 8 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com synchronous-burst read cycle t scvkh t khscx t ghqx burst read cycle t evkh t khex read cycle t glqv t glqx t khqx dq g\ ex\ adv\ bwx\, gw\ t ghqz t khkh t khkl t spvkh t khspx t avkh t khax adsp\ addr adsc\ clk t klkh t khqv t khqx t avvkh t khavx
edi2cg472128v 9 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com synchronous (non-burst) write cycle write cycle timing parameters 8.5ns 10ns 12ns 15ns description sym min max min max min max min max units clock cycle time t khkh * * 15 15 20 ns clock high time t khkl **5 5 6 ns clock low time t klkh **5 5 6 ns address setup t avkh * * 2.5 2.5 2.5 ns address hold t khax * * 1.0 1.0 1.0 ns bank enable setup t evkh * * 2.5 2.5 2.5 ns bank enable hold t khex * * 1.0 1.0 1.0 ns global write enable setup t wvkh * * 2.5 2.5 2.5 ns global write enable hold t khwx * * 1.0 1.0 1.0 ns data setup t dvkh * * 2.5 2.5 2.5 ns data hold t khdx * * 1.0 1.0 1.0 ns t ghkh t gwlkh t avkh t dvkh write cycle oe\ gw\ addr clk ce\ addr 1 addr 1 addr 2 t klkh t khkh t khkl back to back writes t khgh t khdx t khgwh t khax dq ex\ g\ *tbd
edi2cg472128v 10 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com synchronous-burst write cycle burst - late write - cycle t evkh t khex early write cycle t dvkh t khqx dq g\ ex\ adv\ bwx\, gw\ t khkh t khkl t avkh t khax adsp\ addr adsc\ clk t klkh t khqx t avvkh t khavx
edi2cg472128v 11 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com synchronous (non-burst) read/write cycle write cycle t dvkh back to back cycles g\ controlled d (addr 2) gw\ dq q (addr 1) read cycle t khqx t avkh g\ addr ce\ clk t khqv addr 1 addr 2 t khdx t khkh t klkh t khkl t khdx ex\
edi2cg472128v 12 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com package description: 168 gold lead dimm ordering information part number organization voltage speed (ns) package edi2cg472128v85d2* 4x128kx72 3.3 8.5 168 gold lead dimm EDI2CG472128V10D2* 4x128kx72 3.3 10 168 gold lead dimm edi2cg472128v12d2 4x128kx72 3.3 12 168 gold lead dimm edi2cg472128v15d2 4x128kx72 3.3 15 168 gold lead dimm *consult factory for availability package no. 410 u1 u5 u2 u6 u3 u7 u4 u8 .050 .004 .160 min. .195 max. .157 (2x) .078 (2x) .450 1.450 .125 1.700 2.150 .050 typ. .700 5.255 max. 1.00 max. .250 (2x) p1 199 p85 all dimensions are in inches

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